Feature sizes of integrated circuits are continuously decreasing in order to increase the packing density of the various semiconductor devices formed thereby. With this size reduction, however, various steps within the integrated circuit fabrication process become more difficult. One such area within the semiconductor fabricating process that experiences unique challenges as feature sizes shrink is photolithography.
Photolithography involves selectively exposing regions of a resist-coated silicon wafer to form a pattern thereon. Once exposure is complete, the exposed resist is developed in order to selectively expose and protect the various regions on the silicon wafer defined by the exposure pattern (e.g., silicon regions in the substrate, polysilicon on the substrate, or insulating layers such as silicon dioxide).
An integral component of photolithography or a pattern transfer system is a reticle (often called a mask) that includes a pattern thereon corresponding to features to be formed in a layer on the substrate. A reticle typically includes a transparent glass plate covered with a patterned light blocking material, such as chrome. The mask is placed between a radiation source producing radiation of a pre-selected wavelength (e.g., ultraviolet light) and a focusing lens which may form part of a stepper or “step and repeat” apparatus. Placed beneath the stepper is the resist-coated silicon wafer. When the radiation from the source is directed onto the reticle, light passes through the glass (in the regions not containing the chrome mask patterns) and projects onto the resist-coated silicon wafer. In this manner, an image of the reticle is transferred to the resist.
The resist (sometimes referred to as the “photoresist”) is provided as a thin layer of radiation-sensitive material that is typically spin-coated over the entire silicon wafer surface. The resist material is classified as either positive or negative depending on how it responds to the light radiation. Positive resist, when exposed to radiation becomes more soluble and is thus more easily removed in a development process. As a result, a developed positive resist contains a resist pattern corresponding to the dark regions on the reticle. Negative resist, in contrast, becomes less soluble when exposed to radiation. Consequently, a developed negative resist contains a pattern corresponding to the transparent regions of the reticle.
It is well known in the art of photolithography that light passing through the reticle is refracted and scattered by the edges of the chrome mask patterns of the reticle, causing the projected image to exhibit some rounding and other forms of optical distortion. As feature scaling trends continue, variations of feature critical dimensions may no longer be ignored in present day circuit layouts. The problem highlighted above becomes even more pronounced in integrated circuit designs having submicron feature sizes near the wavelength of the radiation employed in the photolithographic process.
In addition, the diffraction and scattering of the radiation in the distorted illumination pattern propagates through the developed resist pattern and negatively impacts the integrated circuit features, such as polysilicon gate regions, vias in dielectrics, etc. As a result, integrated circuit performance is often degraded.
To mitigate this problem, a reticle correction technique known as optical proximity correction (OPC) has been developed. OPC involves the adding of dark regions to and/or the subtracting of dark regions from portions of a reticle to mitigate the distorting effects of diffraction and scattering. Typically, OPC is performed on a digital representation or simulation of a desired integrated circuit pattern. The digital representation is often referred to as the mask layout data and is used by the reticle manufacturer to generate the reticle. First, the mask layout data is evaluated with software to identify regions where optical distortion will result. Then the OPC is applied to compensate for the distortion. The resulting pattern is ultimately transferred to the reticle glass.
Various corrections or modifications are made to the base features of the design layout. Some OPC correction takes the form of “serifs.” Serifs are typically small, appendage-type addition or subtraction regions typically made at corner regions or other areas on reticle designs to compensate for the optical distortions produced by the imaging effects.
In addition, variations in the photoresist and other such imaging material processing cause damage to the features as fabricated, and degradations from the layout design add to the CD variation and failure rate of a targeted CD for a feature. Imaging material processing is complex and difficult to model in OPC designs. Further, other post patterning processes such as etch and cleaning operations are equally difficult to model in OPC designs and cause substantial CD variation.
In the prior art, OPC models rely on standardized symmetrical structures with various fixed pitches. As illustrated in prior art FIG. 1, anchor data 100 comprises a set of features or line elements 115 in a standard symmetrical structure. The features 115 and spaces 120 are evenly distributed having a fixed pitch 125 that may vary as needed between several such anchor data structures 100 (wherein each set of anchor data is symmetrical). These symmetrical structures 100 work well for correcting optical effects via OPC where the RMS errors produced may be averaged over a large sampling set. However, such prior art methods and symmetrical structures 100 do not provide adequate correction for post processing such as etch and clean processes or imaging material processing such as photoresist processes. In addition, standardized symmetrical structures 100 employed in prior art OPC models do not distinguish between the various asymmetric structures that may be relevant to the device layout.
Accordingly, as illustrated in FIG. 2, a typical design layout 200 may possess asymmetrical structures 205 in addition to symmetrically spaced structures similar to structure 100 of FIG. 1. Asymmetric structures 205 comprise, for example, both dense spacing P1 and semi-isolated feature spacing P2. As a result, the asymmetrical structures 205 may show higher failure rates for missing targeted CDs on silicon when these structures are sized utilizing an OPC model based primarily on standard symmetrical structures (e.g., 100 of FIG. 1) having a fixed pitch.
Accordingly, there is a need for a method of optimizing the size of features on silicon utilizing an OPC design that incorporates the effects of post pattern processing and both symmetric and asymmetric feature density spacing effects wherein feature CD and device performance may be improved in the manufacture of semiconductor devices.